Deskripsi

Job description

Semiconductor logic design, verification and tool development

• Tool development: Development of simulation accelerators that greatly improve development/verification efficiency and automatic test pattern generation at the function level (including GUI and HW-IP) based on actual experience
• Commissioned work: RTL design based on customer requirements, creation of verification specifications, verification
• Work environment :Linux/UNIX
• Language: SystemVerilog, Verilog-HDL, VHD C/C++, Python
• Simulator EDA: Various EDA such as VCS, IES, QuestaSIM and formal verifier
• Requirements:
• Have experience, learning experience, or are interested in Digital LSI FE (Front End) design and FPGA FE design
• Have FPGA development experience (classes are also possible)
• Have basic knowledge of electronic circuits

• Monthly income of 220,000 yen or more
• Complete annual salary system (based on experience, ability, etc.)
• Profit return type bonus system and stock option
• Flextime system, standard 8 working hours

• Yokohama City, Kanagawa Prefecture (Headquarters), Soraku-gun, Kyoto Prefecture (Technical Center)
• Remote office possible (depending on ability)